FAQ Overview

Due dates are described on the schedule provided on Canvas by the time of the first lecture, which will apply unless changes are made in response to unforeseen problems that require extensions. The exact day and time is usually set on the Canvas assignment, with the syllabus schedule providing an overview.

Check-off deadlines are described in the syllabus.  Always check the current semester's information, as it occasionally changes.

No. There is no need to attend your lab section prior to the first lecture. See Canvas or Piazza for breaking information at the start of a new semester, including what needs to be done online.

Note the distinction here between the first week of the course and the first week of labs. Nothing is in-person before the first lecture, but read all announcements and other information on Canvas immediately, because there are things to do online in the first week of the course.

Yes. See the course syllabus for details.

After the quiz (the first 15-20 min.) and other assessment (practical exercises), students from other sections are admitted as space permits on a first-come, first-served basis.  Check with the GTA when you enter the lab to ensure that the quiz is finished. Also keep in mind that the TAs will have to give priority to the students in their sections.

If you have a question, place the RED cup on top of your oscilloscope and keep working on solving it yourself.  if you need a check-off, place the YELLOW cup on top of your oscilloscope and begin working on the next section.

In order to avoid any conflicting information, this information appears in only one location:

• due dates: within Canvas, customized for your lab and lecture section
• how late: in the syllabus
• penalties: in the syllabus

Repeating it here or anywhere else is likely to cause confusion when semester-to-semester varations occur.

See the OIT instructions for Windows or for Macs.

In Quartus II, you compile projects, not files. The project must have a top-level file which can include any number of other files in a hierarchical fashion. So, the answer is that you effectively compile the project, which refers to a single top-level file, which in turn includes all needed subcomponents. 

In somewhat more detail, what Quartus will do is start with your top-level design file, and compile everything that it finds as it descends into the structure of that file. Even if you failed to specify a file as part of your design, Quartus will find it IN THAT DIRECTORY and compile it. If it is not in that directory or a designated "library folder," you'll get an error -- so you would have to either tell Quartus to look in other "library folders" or just move the file.

Perhaps even more arcane is to note that if you specifically add a file to the project (on the Navigator pane, for example), Quartus will compile it even if it is not needed by the top-level design file.

The intent of the all-Windows software policy is not meant to be punitive for students nor to support certain software vendors, but merely to provide a common set of tools and a consistent set of instructions. That being said, you can do whatever makes your life easier and still produces the desired results, as long as you realize that other software is not supported directly by the faculty and TAs of ECE 2031. Along those lines, you can use other word processing software, including tools that run on other operating systems.

A common alternative for the Quartus software, suitable for Mac and Linux users, is to access the ECE Virtual Labs (see next question and answer). Another is to use a virtual machine approach on your own computer.

Specifically related to Macs, make sure you see the related FAQ: http://www.powersof2.gatech.edu/faq/index.php?sid=302&lang=en&action=artikel&cat=2&id=15&artlang=en

On the technical side, it is possible to run Quartus natively on Linux, though we have heard that there can be difficulties connecting to the development boards and running the simulator.

The main hurdle is installing the driver.  The driver is typically only installed when a board is first connected, and usually does not install automatically.  Current instructions will be provided in the lab material for the current semester.

Several optios have worked for students in the past:

• Installing Quartus through a Bootcamp Windows setup.
• Use the ECE-provided virtual lab client and access ECE hosts (a very low overhead option, since the client is minimal).   See http://www.ece-help.gatech.edu/labs/virtual.html. There have been issues with the virtual lab setup not always having support for all features, such as missing devices, library components, etc. Contact help@ece.gatech.edu if you have problems, but be very specific.
• Use Parallels Desktop to create a Windows VM and install Quartus there. See http://blog.terasic.com/running-quartus-ii-with-a-mac-no-problem/
• Same, but with VMware instead of Parallels
• Same, but with VirtualBox.

Intel can change their site structure at any time, so you should always search for the current official source of software, either starting with a search engine or on Intel's main website.

In general, you should not be getting errors when you compile a project, and there is usually something to fix. Read the entire message carefully -- it is more useful than students usually realize.
Warnings are another matter. Unfortunately, the lab manual instructions sometimes (as in the tutorial) tell students that they should not get warnings, but that is not necessarily true, even for those early designs. There are really two reasons why you may be getting warnings even when the instructions say you should not:

1. Software updates changed the warnings that are produced by Quartus, since the instructions were written.
2. User preferences in a particular Quartus installation may have changed which severity of warnings are hidden or displayed.

The few warnings that show up in the tutorial are probably not an issue. That actually answers the main question most students have about warnings. But some students actually want to know more about the common warnings, so read on.

• Found [nn] output pins without output pin load capacitance assignment. -- This almost always occurs. It's beyond the scope of this course, but even though the FPGA pins are TTL compatible, producing the correct high and low logic levels, it really depends on what exactly is connected to the FPGA pins.  The DE2 board was designed by people who knew what they were doing.  Quartus doesn't know your target FPGA is on a board designed by people who knew what they were doing.  It is warning you that you haven't given it detailed information that would allow it to calculate if the outputs will change as fast as they should. (Higher capacitance on a pin means more electrons have to flow to make the voltage change, and it takes longer.)
• Not all pins in bus "SW[17..0]" are used.  (Or some other signal besides SW, with some other pin number range).  This means exactly what it says.  You seem to have wanted to use some pins that have a meaningful group, but you left some out. Quartus wants you to make sure that's what you meant.
• Warning: Design contains nnn input pin(s) that do not drive logic. Quartus knows about some input pins, but doesn't see where they are actually used.  The most common occurrence is the one mentoned above.  It could be an indication of a real problem, though (for example), where you added an input pin for something called CLOCK, never actually used it, and connected the CLOCK input on your flip flops to something entirely wrong.   It would compile with no errors, because the CLOCK inputs were driven by something. But it wouldn't be what you intended.
• Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.  You don't need this feature. You don't need a lot of the capability of Quartus, for that matter.  There's no time to learn it in one semester.
• Warning: Ignored locations or region assignments to the following nodes. Later, students may be provided with project files where some of the work of assigning pins has been done for them.  There may be some pins assigned that aren't actually used in the design project.  Quartus is telling you about that.
• Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Related to the previous.
• Warning: Using design file filename.ext, which is not specified as a design file for the current project, but contains definitions for nnn design units and mmm entities in project . Ideally, when you have a project with multiple design files (a hierarchical design with a top-level file and various files "inside" that), you have taken care to specifically add every file to the project (in the Project Navigator "Files" window pane, or under "Project...Add/Remove Files..."   If you don't do that, but if the needed design files are right there in the folder where Quartus expects them, it will compile successfully and give you this warning that you didn't do the Add Files thing.

(The bookstore is no longer used for parts kits, but this information is still relevant.)

You can find the protoboard (breadboard), wire kit, and TTL-compatible parts at electronic retailers. Eta Kappa Nu, the ECE honor society, usually sells these items, and information is forwarded to students as soon as it is available.  By mail order, you can try www.jameco.com and www.digikey.com or others. All parts must be DIP packages (i.e., not SOIC or other surface mount variations). Following are some part numbers. These are subject to change and provided only as a courtesy to students, so check before you order. There may be other equivalent parts at the same vendors, if these are not in stock. These vendors will ship overnight.

If you have a kit from another class and wish to reuse it, compare it with the list below. In particular, the ECE2020 kit is missing the 4-input NAND gate, the 74xxx20. (See the reading for Lab 2 to understand more about HCT/LS distinctions.)

Always get reference information from the official source, starting either with a search engine or with Intel's main website.

Each semester, they are included in the syllabus & course information on Canvas.  If you are not a current student, email the instructor(s).

The course syllabus is on Canvas, and it describes the course assignments and weights for the current semester.

No. There is no need to attend your lab section prior to the first lecture. See Canvas or Piazza for breaking information at the start of a new semester, including what needs to be done online.

1.) Check the Syllabus & Course Information on Canvas.
2.) Check Piazza.
3.) Email your GTA and/or LTA. If they are unable to answer, check with Kevin Johnson or Dr. Collins.

In order to avoid any conflicting information, this information appears in only one location:

• due dates: within Canvas, customized for your lab and lecture section
• how late: in the syllabus
• penalties: in the syllabus

Repeating it here or anywhere else is likely to cause confusion when semester-to-semester varations occur.

We're always happy when students are interested in being a TA for the course!  Please email the instructors for information on how to apply.

The intent of the all-Windows software policy is not meant to be punitive for students nor to support certain software vendors, but merely to provide a common set of tools and a consistent set of instructions. That being said, you can do whatever makes your life easier and still produces the desired results, as long as you realize that other software is not supported directly by the faculty and TAs of ECE 2031. Along those lines, you can use other word processing software, including tools that run on other operating systems.

A common alternative for the Quartus software, suitable for Mac and Linux users, is to access the ECE Virtual Labs (see next question and answer). Another is to use a virtual machine approach on your own computer.

Specifically related to Macs, make sure you see the related FAQ: http://www.powersof2.gatech.edu/faq/index.php?sid=302&lang=en&action=artikel&cat=2&id=15&artlang=en

On the technical side, it is possible to run Quartus natively on Linux, though we have heard that there can be difficulties connecting to the development boards and running the simulator.

In order to avoid any conflicting information, this information appears in only one location:

• due dates: within Canvas, customized for your lab and lecture section
• how late: in the syllabus
• penalties: in the syllabus

Repeating it here or anywhere else is likely to cause confusion when semester-to-semester varations occur.

No. There is no need to attend your lab section prior to the first lecture. See Canvas or Piazza for breaking information at the start of a new semester, including what needs to be done online.

Note the distinction here between the first week of the course and the first week of labs. Nothing is in-person before the first lecture, but read all announcements and other information on Canvas immediately, because there are things to do online in the first week of the course.

Intel can change their site structure at any time, so you should always search for the current official source of software, either starting with a search engine or on Intel's main website.

Always get reference information from the official source, starting either with a search engine or with Intel's main website.